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Flash Memory Controller
Table 6-4. Flash Options register (FOPT) field descriptions (continued)
Bit(s)
10
9:8
7:6
5
4
3
2
1:0
Field
MECFB
CHECKB
—
PW
PROTB
—
SSW
SSC
Description
Mass Erase on CRC Failure
A control bit for the ROM boot function. It is only applicable if CHECKB = 01 or 10. In those cases, if
the CRC check fails and MECF=0, then the user portion of the flash memory will be erased.
This bit provides additional protection of customer code from hacker attempts to bypass security via
“interrupted” erase operations.
This bit is initialized to Bit 2 of flash location 0x3FFE by the boot ROM on power-up. It is read by the
ROM code in a later step of the reset process.
1 Do nothing.
0 Erase the user portion of the main flash array.
Perform Flash Checksum
A control bit for the ROM boot function. It controls whether or not a flash checksum is computed and
checked against expected results before transferring control to code executing in flash. This field is
loaded from location 0x3FFE by the ROM bootloader on POR only. It can be modified via software and
will affect operation during subsequent non-power-on reset sequences.
00 Do not perform checksum.
01 Perform checksum on POR only.
10 Perform checksum on any reset.
11 Do not perform checksum.
Reserved
PROTB Writeable
The PROTB bit can be written from software only when PW = 1. If PW = 0, it must first be reset to 1
before PROTB can be modified.
Active Low Write Protect
Used to inhibit programming and erase operations.
This bit can only be written when PW = 1.
0 Array is protected from unintentional program/erase operations .
1 Array is not protected from unintentional program/erase operations.
Reserved
Security State Writeable
The SSC bit field can be written from software only when SSW = 1. If SSW = 0, it must first be reset to
one before SSC can be modified.
Security State Code
Determine the security state of the MCU. When the MCU is secure, the contents of flash memory
cannot be accessed by instructions from any unsecure source including the background debug
interface.
These bits can only be written when SSW = 1. Security can be temporarily cleared by setting these bits
to 11, however, they will be re-initialized from NVOPT on every reset. These bits are initialized from bits
1:0 of flash location 0x3FFF during each reset sequence.
These bits are initialized to 10 (Secure) by when the peripheral reset is asserted. The flash wrapper will
almost immediate overwrite them as the module exits reset.
00 Unsecured
01 Unsecured
10 SECURE
11 Unsecured
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
67
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